[En-Nut-Discussion] Ethernut 2.0 Alpha Schematic

[Austin Schutz]

> >         This time by writing to any of 0x8000-0x83ff you would switch the
> >16k banks, and any other memory mapped devices would connect off the
> >multiplexor. You could attach one or more ethernet devices, plus any other
> >devices. 4to16 might be more than you want - it will segment the
> >0x8000-0xbfff in 1k blocks. Maybe 3to8 would be better?
> >         Are 16k memory banks large enough? I would tend to think they are.
> 
> 16k memory banks is exactly what I had in mind. But
> I have no idea about how to wire the address lines
> to the RAM, specially A14. Would you mind adding the
> KM684002 form library memory-samsung?
> 

	Sure. Ok, this is the ugliest one yet. :-) I should really figure
out how to do those neat diagrams where a whole bus is combined into one fat
line.

	This takes a little explaining:

	The decoder is only enabled when A14 and A15 are high (0xc000-0xffff).
	The SRAM is enabled whenever the decoder isn't (0x0000-0xbfff).

	The latch's output is enabled when A15 is high and A14 is low
(0x8000 - 0xffff, but the SRAM isn't enabled past 0xbfff). As mentioned,
you will probably need to tie grounded resistors to the latch's output pins
to force the bus low when the latch isn't enabled in order to access low
memory.

	The latch's input is enabled when the decoder is enabled, it is
asserting pin 1/, and the mcu is asserting WR/. (write to 0x8000-0x83ff).

	The 74xx02 NOR could probably be replaced with a NAND and a few
NOTs, saving a chip but adding to the ugliness of the schematic. Also I
haven't looked as the speed of the devices. It looks like the slowest part
is probably setting the latch to output (or not output) in time. The latch
input depends on more devices settling, but it has until the end of the
WR/ cycle to read the input, so it's probably ok.

	Austin
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