[En-Nut-Discussion] Ethernut 2.0 Alpha Schematic

[Harald Kipp]

Here's my version of address decoding:

CS = SRAM chip select
BSx = Bank select register outputs
SAx = SRAM address lines
Ax = CPU address lines

CS = !(A14 & A15);
SA18 = BS4 & A15;
SA17 = BS3 & A15;
SA16 = BS2 & A15;
SA15 = BS1 & A15;
SA14 = (BS0 & A15) # (!A15 & A14);

& means logical and
# means logical or
! means logical negation

Looks correct to me. Would you agree?

Note, that this doesn't include bank
select register addressing, just SRAM.

The low 32k SRAM is always visible at 0x1100 to
0x7FFF. The remaining 30 pages of 16k each are
mapped at 0x8000 to 0xBFFF. From 0xC000 to 0xFFFF
the SRAM is deselected (z-state). Of course, real
chips use !CS.

All remaining addresses A0 to A13 are directly
connected to SA0 to SA13.

I think using gates instead of z-state register
outputs with pull downs could be better transformed
to a CPLD. But I don't know much about CPLD
capabilities.

Harald