[En-Nut-Discussion] Wait-states bug?

[Mikael E.Pedersen (MEP)]

Hi.

I have found the following code in the main() function in init.c:

    outp(BV(SRE) | BV(SRW), MCUCR);

As there are no SRW bit in Mega128 (now called SRW10), and as the register
XMCRA doesn't get addressed at all,
my guess is that this is a leftover from Mega103. Is that correct?
And if it is, what should the correct waitstate value be for acccess to the
SRAM and ethernet controller?
As it is now (SRW10 set and the entire XMCRA register = 0), it results in
one waitstate.
I have tried without waitstates at all, and it seems to run just fine.

Best regards,
Mikael Ejberg Pedersen