AW: [En-Nut-Discussion] waitstates in ethernut?

[Oliver Schulz]

Hi Thomas,

if you mean wait states for external memory access, you can find the
matching instruction in /os/nutinit.c in line 150.

It is:     outp(BV(SRE) | BV(SRW), MCUCR);
By writing the MCUCR register with this value, the external memory interface
is enabled (SRE) with one wait state (SRW) per memory access.

The only onboard peripherals on Ethernut 1.3F is the realtek ethernet
controller. It uses the address space from 0x8300 to 0x831F and the
interrupt line is hard-wired to pin PE5 at the µC, which is INT5. But even
if you don't use ethernet, you can't use the PE5 as input or output pin.

Feel free to connect your own developed peripherals, but don't use addresses
below 0x8000, or the ethernet controller address range.

Cheers,
Oliver.

-----Ursprüngliche Nachricht-----
Von: en-nut-discussion-bounces at egnite.de
[mailto:en-nut-discussion-bounces at egnite.de]Im Auftrag von Thomas Mørch
Gesendet: Montag, 24. November 2003 19:04
An: en-nut-discussion at egnite.de
Betreff: [En-Nut-Discussion] waitstates in ethernut?


I have been looking through the documentation for the ethernut project,
searching for waitstates.

But so far without luck.. So anyone here that can enlighten me on this
subject?

Another thing, I miss a memory layout for the onboard peripherals of the
ethernut (ethernet controler and so on).

I have a ethernut 1.3F

/ Thomas