[En-Nut-Discussion] Ethernut CF (WLAN) Interface

[Michael Fischer]

Hello,

I think you have read the last thread about the Ethernut IDE/CF Interface.
The problem was (is) that the Netgear MA401 is using the WAIT signal.

Therefore I have now a new prototype with a bigger Xilinx. All the signals
are
pass-through the CPLD. This has the effect that I can use it as a level
shifter
for 3.3 and 5.0 voltage.

But the "problem" with the WAIT still exist. Now I emulate the bus access.
That mean the CPLD have several register and use an address range of 4
bytes.

To make a write access to the MA401 you must use the follwing source:

/************************************************************/
/*  WriteXXX                                                */
/************************************************************/
static void WriteXXX (WORD wAddress, WORD wData, MEMORY_TYPE eIO)
{
  /*
   * set ADDRESS
  */
  ADDRESS_LOW_REG  = LOBYTE(wAddress);
  ADDRESS_HIGH_REG = HIBYTE(wAddress);

  /*
   * set DATA
  */
  DATA_LOW_REG  = LOBYTE(wData);
  DATA_HIGH_REG = HIBYTE(wData);

  /*
   * set CE1, CE2
  */
  CTRL_REG     = (CTRL_CE1 | CTRL_CE2 | CTRL_OE | CTRL_WE | CTRL_IORD |
CTRL_IOWR | CTRL_DATA_OUT);

  /*
   * set WR/IOWR
  */
  if (eIO == TYPE_MEM) {
    CTRL_REG   = (CTRL_CE1 | CTRL_CE2 | CTRL_OE |           CTRL_IORD |
CTRL_IOWR | CTRL_DATA_OUT);
  } else {
    CTRL_REG   = (CTRL_CE1 | CTRL_CE2 | CTRL_OE | CTRL_WE | CTRL_IORD |
CTRL_DATA_OUT);
  }

  /*
   * check the WAIT signal
  */
  //Do some code here

  /*
   * remove WR/IOWR
  */
  CTRL_REG     = (CTRL_CE1 | CTRL_CE2 | CTRL_OE | CTRL_WE | CTRL_IORD |
CTRL_IOWR | CTRL_DATA_OUT);

  /*
   * remove CE1, CE2
  */
  CTRL_REG     = (                      CTRL_OE | CTRL_WE | CTRL_IORD |
CTRL_IOWR);
}


But this takes to long, up to 1,5us for an access.

How can we solve this problem now?

1. Use the old way, direct mem/io access to the card. But
use the function XDIV of the CPU. Divide the clock down to 3Mhz
and hope the card get no problem. This was my first try with the
first prototype.

2. Build a state machine in the CPLD. Which handle the access.
I can imagine the following procedure:

The CF card is a 16bit card, therefore we need to access, like the same as
the IDE interface.
Write the high byte at the odd address, and after this the low byte at the
even address.

The CPLD latch the address and the data. The last write at the even address
start the
state machine in the CPLD. Now the CPLD will do the rest. To check if this
access is ready, there
must exist a ctrl register in the CPLD. We can read this ctrl-reg and if the
access is ready, a bit
it set. I hope this is faster than 1,5us.


Now some words about the source:
I use here the source from FreeBSD, with the 1,5us way. I can access the
MA401
(It is the 5V PCMCIA card). I hope that in the next weeks it is possible to
receive a packet over the air.


Who can help to design the CPLD?
It should be a Xilinx CPLD, because the software is free.
And I use here the Xilinx WebPack 6.1.

Best regards,

Michael