[En-Nut-Discussion] PWM on SAM7X

[Rudakevych, Pavlo]

Any thoughts on what Im doing wrong? Im looking for PWM output on PB20,
and just seeing steady output.
  -pavlo

#include "at91_pwmc.h"
#define LED2 (1<<20) // PB20, PB20_PWM1_A

    outr(PIOB_PDR,LED2);   // set so its periheral, not IO
    outr(PIOB_ASR,LED2);   // set to periheral A
    outr(PIOB_OER,LED2);   // enable output
    outr(PMC_PCER,PWMC_ID); // enable the PWM clock in the PMC (power
managment controller)
    outr(PWM_MR,0x01010101); // clocks
    outr(PWM_CDTY1, 600); // duty
    outr(PWM_CPRD1, 6000); // period
    outr(PWM_CMR1,0x00000002); // CUP modified duty cycle,left align,
MCK/4
    outr(PWM_ENA,(1<<1)); // enable PWM1

Wrote my own at91_pwmc.h:
===================================================================
#ifndef _ARCH_ARM_AT91_PWMC_H_
#define _ARCH_ARM_AT91_PWMC_H_


/*!
 * \file arch/arm/at91_pwmc.h
 * \brief AT91 peripherals.
 *
 * \verbatim
 *
 * $Log: at91_pwmc.h,v $
 *
 * \endverbatim
 */

/*! \name PIO Register Offsets */
/*@{*/
#define PWM_MR_OFF      0x00000000  /*!< \brief PWM mode register
offset. */
#define PWM_ENA_OFF     0x00000004  /*!< \brief PWM enable register
offset. */
#define PWM_DIS_OFF     0x00000008  /*!< \brief PWM disable register
offset. */
#define PWM_SR_OFF      0x0000000C  /*!< \brief PWM status register
offset. */

#define PWM_IER_OFF     0x00000010  /*!< \brief PWM Interrupt Enable
register offset. */
#define PWM_IDR_OFF     0x00000014  /*!< \brief PWM Interrupt Disable
register offset. */
#define PWM_IMR_OFF     0x00000018  /*!< \brief PWM Interrupt Mask
register offset. */
#define PWM_ISR_OFF     0x0000001C  /*!< \brief PWM Interrupt Status
register offset. */

#define PWM_CMR0_OFF    0x00000200  /*!< \brief Channel 0 Mode Register
offset. */
#define PWM_CDTY0_OFF   0x00000204  /*!< \brief Channel 0 Duty Cycle
Register offset. */
#define PWM_CPRD0_OFF   0x00000208  /*!< \brief Channel 0 Period
register offset. */
#define PWM_CCNT0_OFF   0x0000020C  /*!< \brief Channel 0 Counter
register offset. */
#define PWM_CUPD0_OFF   0x00000210  /*!< \brief Channel 0 Update
register offset. */

#define PWM_CMR1_OFF    0x00000220  /*!< \brief Channel 1 Mode Register
offset. */
#define PWM_CDTY1_OFF   0x00000224  /*!< \brief Channel 1 Duty Cycle
Register offset. */
#define PWM_CPRD1_OFF   0x00000228  /*!< \brief Channel 1 Period
register offset. */
#define PWM_CCNT1_OFF   0x0000022C  /*!< \brief Channel 1 Counter
register offset. */
#define PWM_CUPD1_OFF   0x00000230  /*!< \brief Channel 1 Update
register offset. */
/*@}*/

/*! \name PWMC Register Addresses */
/*@{*/
#if defined(PWMC_BASE)
#define PWM_MR      (PWMC_BASE + PWM_MR_OFF)    /*!< \brief PWM mode
registeraddress. */
#define PWM_ENA     (PWMC_BASE + PWM_ENA_OFF)   /*!< \brief PWM enable
register address. */
#define PWM_DIS     (PWMC_BASE + PWM_DIS_OFF)   /*!< \brief PWM disable
register address. */
#define PWM_SR      (PWMC_BASE + PWM_SR_OFF)    /*!< \brief PWM status
register address. */

#define PWM_IER     (PWMC_BASE + PWM_IER_OFF)   /*!< \brief PWM
Interrupt Enable register address. */
#define PWM_IDR     (PWMC_BASE + PWM_IDR_OFF)   /*!< \brief PWM
Interrupt Disable register address. */
#define PWM_IMR     (PWMC_BASE + PWM_IMR_OFF)   /*!< \brief PWM
Interrupt Mask register address. */
#define PWM_ISR     (PWMC_BASE + PWM_ISR_OFF)   /*!< \brief PWM
Interrupt Status register address. */

#define PWM_CMR0    (PWMC_BASE + PWM_CMR0_OFF)  /*!< \brief Channel 0
Mode register address. */
#define PWM_CDTY0   (PWMC_BASE + PWM_CDTY0_OFF) /*!< \brief Channel 0
Duty Cycle register address. */
#define PWM_CPRD0   (PWMC_BASE + PWM_CPRD0_OFF) /*!< \brief Channel 0
Period register address. */
#define PWM_CCNT0   (PWMC_BASE + PWM_CCNT0_OFF) /*!< \brief Channel 0
Counter register address. */
#define PWM_CUPD0   (PWMC_BASE + PWM_CUPD0_OFF) /*!< \brief Channel 0
Update register address. */

#define PWM_CMR1    (PWMC_BASE + PWM_CMR1_OFF)  /*!< \brief Channel 0
Mode register address. */
#define PWM_CDTY1   (PWMC_BASE + PWM_CDTY1_OFF) /*!< \brief Channel 0
Duty Cycle register address. */
#define PWM_CPRD1   (PWMC_BASE + PWM_CPRD1_OFF) /*!< \brief Channel 0
Period register address. */
#define PWM_CCNT1   (PWMC_BASE + PWM_CCNT1_OFF) /*!< \brief Channel 0
Counter register address. */
#define PWM_CUPD1   (PWMC_BASE + PWM_CUPD1_OFF) /*!< \brief Channel 0
Update register address. */
#endif /* PWMC_BASE */
/*@}*/

/*@} xgNutArchArmAt91Pio */

#endif                          /* _ARCH_ARM_AT91_PWMC_H_ */