[En-Nut-Discussion] ARM9 - PLL setup

Alain M. alainm at pobox.com
Wed Aug 20 16:47:36 CEST 2008

Harald Kipp escreveu:
> I intend to have the initial clock settings configurable. Great, if you 
> can provide a diff. I'd apply this first before adding more code to make 
> it configurable.

Ok, I first sent it to Paulo Silva for testing (I don't have the HW here).

BTW, I have full and detailed comments about each initialization, 
including links to the AT91SAM9'a manual. It would be very easy to 
include. Wolut you care for me to include them? Here is a sample:
# Address 0xFFFFFC28 CKGR_PLLAR, PLL A Register cap.26.9.9
# bit 7:0  DIVA=09 Divider output is the Main Clock divided by DIVA
# bit 13:8 PLLACOUNT=0x1F number of Slow Clock cycles before the LOCKA 
bit is set in PMC_SR after CKGR_PLLAR is written.
# bit 15:14 OUTA=10b Clock Frequency Range, from datasheet cap.41.5.5
# bit 26:16 MULA=0x060=96 Multiplier
# bit 29    allways=1
# clock = 18.432*(96+1)/9 = 198.6MHz
# delay = 31/32kHz = 1ms
For me it would be a very nice repository to all this work that is 
already done :)


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