[En-Nut-Discussion] AT91SAM7X256 TC1 Timer being disabled

[Timothy M. De Baillie]

Bernd Walter wrote:
> Interrupts are disabled automatically during interrupt service.
> You need to reenable them after saving old register context and vice
> versa at the end.
> Interrupt routines have a register set of their own, but since you
> can interrupt another interrupt you have to take care about it's
> context.
>
>   
>> Our temporary solution involves using a wrapping timer instead of a 
>> resetting timer.  Additionally, if the timer's accuracy is highly 
>> important, you should check for overflow and handle it (ie: two 
>> interrupts before handler, should be detectable by amount in TC1_CV)
>>     
>
> I fail to see how a missed interrupt can lead to timer stoping.
>   
It has been a while since I looked at it, but basically what happens is 
the OS stops interrupting because the second interrupt is never queued 
and therefore never cleared. Subsequent interrupts on the timer then are 
missed. The timer is still running, it just doesn't cause an interrupt 
in the OS. I have seen this on a logic analyzer and read out the CV 
register which continued to change.

The odd behavior would be TC0 stopping as well. I don't have an 
explanation for that.

> This sounds like a design failure somewhere else.
>   
I agree. We resolved our design failure (other interrupt taking too 
long) and additionally added the "fix" for the timer stopping just 
because we don't want the timer to stop in production code.

Tim DeBaillie