[En-Nut-Discussion] ARM GCC 4.4 Alignment Problems

[Bernd Walter]

On Thu, Apr 01, 2010 at 06:09:28PM +0200, Ole Reinhardt wrote:
> Hi Harald,
> 
> > It looks like the optimizer changed in GCC 4.4.2, specifically access to
> > packed structure elements.
> 
> Just an aditional idea... What about an alignment trap handler? Indeed I
> don't have any code, but I'm quite shure I saw some code on the web...
> Will search again for it.

I'm not so much a fan about missaligned data.
In almost every case it is avoidable without much trouble.
One of the most annoying points with network data is the 6 bytes long
ethernet header, which usually garanties missaligned IP headers, but
usually this is avoided by setting RX buffers at a 2 byte offset or
copying the data before parsing if HW require 32bit aligned DMA RX
buffers - AT91SAM7X should be happy with 2 byte offset, AT91RM9200
are not and require copying.

Packed on ARM has different reasons - older ARM CPUs required bytes
and 16bit words to be on the same alignment because they had to
mask bytes out from 32bit memory operations and therefor structs
containing 3 bytes are 4 bytes long, so that an array of those structs
always start the same members at the same 32bit offset.
Usually this isn't a problem and it is also Ok with C-standards, but
parsing network data with structs can be a problem.
Since we don't need ABI compatibility with older ARM systems it
shouldn't be a problem to use -mstructure-size-boundary=8 (bits)
and don't use packed.

-- 
B.Walter <bernd at bwct.de> http://www.bwct.de
Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.