[En-Nut-Discussion] Missing FMR_EFC1 initialisation

[Krzysztof Sawicki]

Hi!

I've noticed that in arch/arm/os/nutinit.c only one Flash Mode Register 
is initialised which is insufficient for uCs with two flash planes (eg. 
AT91SAM7X512). And some mistakes in comments. Patch follows:

Index: arch/arm/os/nutinit.c
===================================================================
--- arch/arm/os/nutinit.c	(revision 5177)
+++ arch/arm/os/nutinit.c	(working copy)
@@ -169,6 +169,7 @@
          uint32_t freq = NutGetCpuClock();
          /* Set Flash Waite state. */
          outr(MC_FMR, ((((freq + freq / 2) / 1000000UL) & 0xFF) << 16) 
| MC_FWS_2R3W);
+        outr(MC_FMR_EFC1, ((((freq + freq / 2) / 1000000UL) & 0xFF) << 
16) | MC_FWS_2R3W);
      }
  #endif
  #ifdef EARLY_STDIO_DEV
Index: include/arch/arm/atmel/at91_mc.h
===================================================================
--- include/arch/arm/atmel/at91_mc.h	(revision 5177)
+++ include/arch/arm/atmel/at91_mc.h	(working copy)
@@ -99,10 +99,10 @@
  #define MC_FMCN_LSB                     16      /*!< \brief Flash 
microsecond cycle number LSB. */
  #define MC_FMCN_MASK            0x00FF0000      /*!< \brief Flash 
microsecond cycle number mask. */

-#define MC_FCR_EFC0_OFF         0x00000064      /*!< \brief MC flash 
mode register bank 0 offset. */
-#define MC_FCR_EFC0 (MC_BASE + MC_FCR_EFC0_OFF) /*!< \brief MC flash 
mode register bank 0 address. */
-#define MC_FCR_EFC1_OFF         0x00000074      /*!< \brief MC flash 
mode register bank 1 offset. */
-#define MC_FCR_EFC1 (MC_BASE + MC_FCR_EFC1_OFF) /*!< \brief MC flash 
mode register bank 1 address. */
+#define MC_FCR_EFC0_OFF         0x00000064      /*!< \brief MC flash 
command register bank 0 offset. */
+#define MC_FCR_EFC0 (MC_BASE + MC_FCR_EFC0_OFF) /*!< \brief MC flash 
command register bank 0 address. */
+#define MC_FCR_EFC1_OFF         0x00000074      /*!< \brief MC flash 
command register bank 1 offset. */
+#define MC_FCR_EFC1 (MC_BASE + MC_FCR_EFC1_OFF) /*!< \brief MC flash 
command register bank 1 address. */

  #define MC_FCR_OFF         MC_FCR_EFC0_OFF      /*!< \brief MC flash 
command register offset. */
  #define MC_FCR                 MC_FCR_EFC0      /*!< \brief MC flash 
command register address. */

greetings

-- 
Krzysztof Sawicki
Mobile Systems Research Labs, Poznan University of Technology