[En-Nut-Discussion] Scheduling out of Interrupt sometimes take a timertick NAP

[Uwe Bonnes]

Hello,

e.g.the STM32 Spi driver may be used DMA/interrupt driven. When transfer is
finished, the interrupt routine signals the waiting thread via
NutEventPostFromIrq(). The waiting thread then deasserts chipselect. This
can be controlled good with a logic analyser. However I often see a gap of
nearly exact 1 ms between the last sck toggle and the cs deassert. Timertick
is 1 ms. I also have seen these gaps with other similar signaling. I never
saw such a gap with NutEventPost(). These gaps substantial slows down
effective SPI transfer rate, as, b.t.w. also does DMA/interrupt driven SPI
transfers on small chunks with fast rate with regard to polling transfer
due to additional scheduling round trips.

Did anybody else see such gaps?

Can anybody help debugging?

Any idea what may be the cause?

Thanks
-- 
Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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