[En-Nut-Discussion] STM32F756 strange effect

[Uwe Bonnes]

>>>>> "Holger" == Holger Mai <mai at gemac.info> writes:

    Holger> Linkerscript is modified to use RAM from 0x20010000, same value
    Holger> used in configurator, "Memory Start" entry in Kernel section,
    Holger> because the first 64kb RAM is not accesible from DMA (Data RAM,
    Holger> core access only)

Digging more in the configuration, this is where your problem starts. SRAM1
and SRAM2 on the F7 are connected to the AXIM bus and AXIM bus goes through
I/D cache. DTCM does not go through DCACHE, but can do DMA as opposed of
what http://www.nuttx.org/doku.php?id=wiki:howtos:port-drivers_stm32f7
tells.

So DMA with memory from DTCM does _not_ need to care for cache coherency.

When changing the RAM start address away from DTCM, you opened the can of
worm for cache coherency problems. We could solve by disabling DCACHE, at
the cost of much slower "const data" acess or by keeping the RAM layout.

Bye

-- 
Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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