[En-Nut-Discussion] stm32f1_clk.c set systemclock for PLL *6.5

[Uwe Bonnes]

Hello Kontais,

please write to the mailing list as perhaps others may be interested.

>>>>> "kontais" == kontais  <kontais at aliyun.com> writes:

    kontais> Hi Uwe, When a use Makefile.cm3-gccdbg to make a debug file, I
    kontais> get the error output bellow.  the error line is deal with
    kontais> STM32F105x and STM32F107x system clock (PLL input clock x 6.5),
    kontais> need move down after pllinput value set.

Okay. Use SVN Head. This just applied batch of patches mostly reworks clock
setup. This rework should bring F105/7 in a better shape.

Remember to appy the the changes mentioned in my other mail to the mailing
list.

Bye
-- 
Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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