[En-Nut-Discussion] Ethernut 2.0 Alpha Schematic

[Austin Schutz]

On Wed, Oct 23, 2002 at 07:43:47PM +0200, Harald Kipp wrote:
> 
> >         The decoder is only enabled when A14 and A15 are high 
> > (0xc000-0xffff).
> 
> OK.
> 
> >         The SRAM is enabled whenever the decoder isn't (0x0000-0xbfff).
> 
> OK.
> 
> 
> >         The latch's output is enabled when A15 is high and A14 is low
> >(0x8000 - 0xffff, but the SRAM isn't enabled past 0xbfff). As mentioned,
> 
> Wouldn't A14 low and A15 high result in
> 0x8000 to 0xBFFF? Anyway, this won't hurt,
> right?
> 

	You're right. The way I drew it the latch will be enabled
with A14 low and A15 high. That's what I get for working on this late at
night. :) You _could_ output only on A15 high though. In the schematic you
would remove the NAND IC3B and connect the NOT IC1B directly to OC/ on
the latch. One less NAND to think about, and that would also speed up
setting the latch output enable.

> 
> >         The latch's input is enabled when the decoder is enabled, it is
> >asserting pin 1/, and the mcu is asserting WR/. (write to 0x8000-0x83ff).
> 
> This knocks me down completely. Don't we have a
> RAM bank here?

	Oops, you're right again. You actually write to 0xc000-0xc3ff. I
forgot to change that when I changed the schematic.
	Btw, this would be pretty silly to do, but you should be able to
bank switch the low memory too by writing 0x00 and 0x01 to the latch.

	Austin