[En-Nut-Discussion] Ethernut 2.0 Alpha Schematic

[Harald Kipp]

>         The decoder is only enabled when A14 and A15 are high 
> (0xc000-0xffff).

OK.

>         The SRAM is enabled whenever the decoder isn't (0x0000-0xbfff).

OK.


>         The latch's output is enabled when A15 is high and A14 is low
>(0x8000 - 0xffff, but the SRAM isn't enabled past 0xbfff). As mentioned,

Wouldn't A14 low and A15 high result in
0x8000 to 0xBFFF? Anyway, this won't hurt,
right?


>         The latch's input is enabled when the decoder is enabled, it is
>asserting pin 1/, and the mcu is asserting WR/. (write to 0x8000-0x83ff).

This knocks me down completely. Don't we have a
RAM bank here?

Harald