[En-Nut-Discussion] 8019 IOCHRDY question

[Waschk,Kolja]

Hi;

as reported earlier, ignoring the RTL8019AS' IOCHRDY may cause problems and
actually does so under certain circumstances. Are there any experiences
about _which_ operations often cause IOCHRDY to be asserted for longer than
usual? Writing to specific RTL8019AS registers or data transfer in general?

Wouldn't it be reasonable to change the ATmega128 external memory
wait state settings for those operations? Or does it occur especially in
the "DMA" mode during packet data transfer, where lowering the access
speed would impact network thoughput?

On devices such as the 1.3F board (where upper 32K address space isn't
occupied with SRAM) one may even use the ability of the m128 to specify
different wait state configuration for lower and upper part of external
address space permanently.

Kolja


-- 
mr. kolja waschk - haubach-39 - 22765 hh - ger
phone +49 40 889130-34 - fax -35 - e-mail s.a.