[En-Nut-Discussion] 8019 IOCHRDY question

Bengt Florin bengt at florin.se
Wed Jan 21 12:09:25 CET 2004


I recently made measurements of IOCHRDY and sent the results to Harald.


"I connected a logic analyzer to IOCHRDY to see how it works and to my
there where only one occasion where it was active (low).
This was always at the point where the remote DMA is set up for getting the
packet header. So I put a small delay at that place (1us=16 nops) and after
that the
IOCHRDY is gone forever. I have been running for 24h+ and no IOCHRDY.
Also the sanity check is never entered any more.

So after all it seems your HW is definitely NOT BAD!

The driver however can be significantlly improved."

So that's what i'm doing.


-----Original Message-----
From: en-nut-discussion-bounces at egnite.de
[mailto:en-nut-discussion-bounces at egnite.de]On Behalf Of Waschk,Kolja
Sent: den 21 januari 2004 12:03
To: en-nut-discussion at egnite.de
Subject: [En-Nut-Discussion] 8019 IOCHRDY question


as reported earlier, ignoring the RTL8019AS' IOCHRDY may cause problems and
actually does so under certain circumstances. Are there any experiences
about _which_ operations often cause IOCHRDY to be asserted for longer than
usual? Writing to specific RTL8019AS registers or data transfer in general?

Wouldn't it be reasonable to change the ATmega128 external memory
wait state settings for those operations? Or does it occur especially in
the "DMA" mode during packet data transfer, where lowering the access
speed would impact network thoughput?

On devices such as the 1.3F board (where upper 32K address space isn't
occupied with SRAM) one may even use the ability of the m128 to specify
different wait state configuration for lower and upper part of external
address space permanently.


mr. kolja waschk - haubach-39 - 22765 hh - ger
phone +49 40 889130-34 - fax -35 - e-mail s.a.

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