[En-Nut-Discussion] Major memory mapping changes?

[Harald Kipp]

>4. The CPLD picture you posted, look at the top right hand part at the AND
>with A14 and A15 on inputs and SRAMCS on outputs. Does this mean that
>address bits 14 and 15 have to be set to read from the banked memory? If
>so, then it's not mapped to 0x8000 but to 0xC000. This seems weird as the
>NIC (mapped to 0xC000 works fine).

I checked this against the Xilinx project files and
negated RAM select is indeed 'A14 AND A15', which is correct
in my view. It is high as long as A14 and A15 are both
high, which is true for 0xC000-0xFFFF.

Harald