[En-Nut-Discussion] Major memory mapping changes?

[Pavel Chromy]

Hello Radek,

Radek Podgorny wrote:
 
> I thought the address and data bus is connected directly to the MCU.

There _must_ be a latch to obtain 16-bit wide address bus,
as on the MCU side the data lines and half of address lines share the same pins.
Have a look into datasheet, search for ALE signal.

> So
> there is a latch somewhere in between operating at 3.3V? If you're talking
> about the CPLD itself, the 3.3V level it outputs shouldn't matter as long
> as the levels on the "main" bus (the one connected directly to the MCU and
> the pins) is 5V.

Not necessarily, I belive that CPLD is 5V tolerant and even 3.3V singals
reach the MCU theshold.

Pavel