[En-Nut-Discussion] How Ethernut 1.3-Rev. G hardware works?

Rodrigue rodrigue.roland at gmail.com
Sat Oct 28 19:43:01 CEST 2006


I'm trying to figure out how Ethernut 1.3-Rev. G hardware works! I read the
datasheet but I didn't find anywhere why the RTL8019AS is memory mapped at
I think that I've understood how the static RAM, K6X0808C1D, works and
what's the goal of using the 74HC573D. Firstly, we send 8 bits on the data
bus, these bytes are memorized by the latch, and secondly, we send the 7
others bits of the adress on the adress bus; so we have 2^15 ~32ko, we're
able to adress all the memory. What I don't understand is that A15 is used
to enable the memory chip (activated when CE is low) BUT this pin is also
used for the RTL8019AS with an inverter gate, normally it's the EEMU pin
connected to PC7 (the EEPROM emulator output). How do you make to avoid
conflict between the static RAM and the EEPROM emulation? I don't find the
file which contains the source code of read and write to static RAM. I found
nicrtl for RTL8019AS but nothing for the 32ko memory.
Finally, could you explain me how the RTL8019AS works, please? It's
connected in 8 bits data bus (27k resistor on IOCS16B pin) but the adress
bus is 16 bits. I saw that the memory is divided with some buffers (ring
Buffers). When did INT0 raise an interrupt to the int5, PE5, of the
ATMEGA128? Is the pin PE6 used?

Thank you in advance!
Best regards,
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