[En-Nut-Discussion] Ethernut 5.0 Schematic Preview

[duane ellis]

Harald Kipp wrote:
> A new Ethernut 5.0 schematic preview is available for download:
>
> http://www.ethernut.de/pdf/enut5.0-revb_schematic.pdf
>
> As usual, your comments on the hardware layout are highly appreciated
>   
see below.

-Duane.

0) When will boards be available? (in the US)

1) Olimex boards have a nice feature -
    If I set the jumper the right way...
    I can steal +5V from the USB cable from the PC....
    No wall-wart is required.  Will this be a feature of your board?
    Yes, I know, technically it is cheating....

2) - NAND FLASH - Busy output requires a pull up.
    Should be low - 4.7K (not 100K)- otherwise - it takes a long time to 
pull up.
   
3)   SD/MMC - card detect & wp - etc - no pullups?

    Section 6 of SD specific says SD interfaces must have pull ups on 
*ALL* data pins.
    (in addition to the CMD pin)

    
http://www.sdcard.org/about/memory_card/pls/Simplified_Physical_Layer_Spec.pdf
    [Above is a "simplified specification", the full version has this info]

    This page - seems correct and has that detail.
    
http://www.digitalspirit.org/file/index.php/obj-download/docs/sd/TOSHIBA_SD_Card_Specification.pdf

    Section 6.4 (PDF page 13 of 50) show the schematic.
    and list R(data) & R(cmd)  (page 14 of 50, table 7) as 10K to 100K.
   

4)   Do you have a "proposed layout" for this board?

5)   Why is JTAG a non-standard connector? (not 20pin?)
       Or I'm very confused about what JP2 is.
        RTCK for all ARM "S" type cores should be on the jtag connector.
       Otherwise - adaptive clocking does not work.

        Same with NTRST - the "tap" reset - as compared to NRST (cpu reset).
       There is a game you can play in jtag, ie: hold NRST - and NTRST
       release NTRST - take control of the Jtag tap, and the CPU then 
release
       the CPU reset... in the present configuration that does not 
appear to be possible.

        The RTCK issues is critical if you want to debug low power 
shutdowns.
        Or dynamic power management stuff.
        Otherwise - JTCK must be 1/6 of the dynamic CPU core clock.
        Whatever that may be at that moment in time.
   
       I learned these things debugging low power things in ebook platforms.
      
6)    Other eval boards - and yes, I know this is not an eval board...
       have a series of 0.1 center holes - nicely configured so you can 
get at the various gpio pins.
       take a look at the new cortex ones from ST.
      
       Example the PA23/24 - for the i2c chip.
       two solder points - or a 2pin connector - (or 4pin, ie: 
gnd/3.3/sda/sdc)
        not populated on the pcb would so I can add more would be nice.

7)  No coin cell for the RTC?
    Or are you just charging a super-cap?