[En-Nut-Discussion] Ethernut 5.0 Schematic Preview

[Harald Kipp]

duane ellis wrote:
> Harald Kipp wrote:
>> A new Ethernut 5.0 schematic preview is available for download:

> 0) When will boards be available? (in the US)

Depends on how well the prototype will do, which we expect to have ready 
within the next 2 weeks.

> 1) Olimex boards have a nice feature -
>     If I set the jumper the right way...
>     I can steal +5V from the USB cable from the PC....
>     No wall-wart is required.  Will this be a feature of your board?
>     Yes, I know, technically it is cheating....

No jumper required. The power management CPU will prioritize the supply 
channel. By default it is

1. 5-24V DC
2. PoE
3. USB


> 2) - NAND FLASH - Busy output requires a pull up.
>     Should be low - 4.7K (not 100K)- otherwise - it takes a long time to 
> pull up.

You're right, thanks.


> 3)   SD/MMC - card detect & wp - etc - no pullups?

The internal CPU pull-up can be used.


>     Section 6 of SD specific says SD interfaces must have pull ups on 
> *ALL* data pins.
>     (in addition to the CMD pin)

I assume that this will be handled well by the CPU. Actually I followed 
the AT91SAM9XE-EK schematic. But I'll check this again.


> 4)   Do you have a "proposed layout" for this board?

I'm working on this. In general the geometry will follow existing Ethernuts.

> 5)   Why is JTAG a non-standard connector? (not 20pin?)
>        Or I'm very confused about what JP2 is.
>         RTCK for all ARM "S" type cores should be on the jtag connector.
>        Otherwise - adaptive clocking does not work.

All Ethernuts do have the same JTAG connector. For historical reasons 
they use the AVR layout, which doesn't provide RTCK, but a spare pin. 
This one can be used for RTCK by connecting pins 3 and 4 of JP2.

>         Same with NTRST - the "tap" reset - as compared to NRST (cpu reset).
>        There is a game you can play in jtag, ie: hold NRST - and NTRST
>        release NTRST - take control of the Jtag tap, and the CPU then 
> release
>        the CPU reset... in the present configuration that does not 
> appear to be possible.

Never heard about this. Until today my opinion was, that NTRST is not 
required except on some faulty JTAG hardware.


>         The RTCK issues is critical if you want to debug low power 
> shutdowns.
>         Or dynamic power management stuff.
>         Otherwise - JTCK must be 1/6 of the dynamic CPU core clock.
>         Whatever that may be at that moment in time.

I agree on this one. However, as far as I can say, it is not supported 
on the OpenOCD/FTDI combination. Anyway, RTCK may be available at pin 8.


> 6)    Other eval boards - and yes, I know this is not an eval board...
>        have a series of 0.1 center holes - nicely configured so you can 
> get at the various gpio pins.
>        take a look at the new cortex ones from ST.

I'm afraid, there will be no space for this. The expansion port will 
provide this and, when carefully layed out, the same hardware will run 
on AVR and ARM based Ethernuts.


>        Example the PA23/24 - for the i2c chip.
>        two solder points - or a 2pin connector - (or 4pin, ie: 
> gnd/3.3/sda/sdc)
>         not populated on the pcb would so I can add more would be nice.

May be in the final layout there is some space left for a minimal area.


> 7)  No coin cell for the RTC?
>     Or are you just charging a super-cap?

The main thing I like with supercaps is the absence of maintenance. They 
don't care about complete discharge, while batteries provide a lot of 
problems here. Further, batteries require special declarations when 
shipping them.

We thought about adding a lithium connector to be able to run the CPU on 
battery. But the power supply is already very complicated and there is a 
point where you have to decide to stop development and start with the 
real board. May be on Ethernut 5.1.

Many thanks for your valuable comments,

Harald