[En-Nut-Discussion] Address space of EIR

[tgrauss at free.fr]

Hello,

I am looking at the schematic of the EIR board and there is something I find
strange ...
How can I use the address bus on this board? The A0 bit is used for DQML and not
as an address line. So the address is from A1 to A15 instead of A0 to A15. I can
understand from A0 to A14 (15 bits instead of 16 bits addressing).
Also, for the RAM, instead of using PB12, we use PA24?? I guess this is linked
to the 0x2000 0000 - 0x23FF FFFF address space of the RAM.
Why the address range of the RAM is shifted of 2 bits toward the MSB?

For short, should I just connect my devices using the address lines from PB0 to
PB15 and just be careful to be in the free address space described in the
documentation of the EIR board (0x1000 0000 - 0x1FFF FFFF, 0x5000 0000 - 0x8FFF
FFFF). Also, in the doc, for 0x5xxx xxxx, it is said that chip select 4 is
availlable ... isn't it chip select 5?

Thank you in advance for your answers.

Regards

Thierry