[En-Nut-Discussion] Many thanks to the creators and maintainers of Ethernut...

[Harald Kipp]

Jim Patchell wrote:
> It was based on the 
> Ethernut 2.1b dev board, with changes such as using an Actel FPGA (which 
> will be where the hardware portion of my application will live), plus it 
> takes the place of the Xilinx CPLD...

Cool. Did you do the banked memory register in Verilog? If yes, would
you be willing to contribute it under BSD license?

You may know, that Ethernut 3 got a larger CPLD, which includes an MMC
interface. We have all tools to compile Verilog into XSVF and upload it
together with a small utility (called XsvfExecutor) to the target via
Ethernet and let the CPU program the CPLD. For Ethernut 3 this works in
one go and is quite convenient, just editing the Verilog source, typing
'make install' and have the new CPLD running within a few seconds.

I'd like to have this available for Ethernut 2 as well, but currently
the CPLD contents is defined as a schematic only, created with the ISE tool.

Harald