[En-Nut-Discussion] Many thanks to the creators and maintainers of Ethernut...

Jim Patchell patchell at cox.net
Fri Jan 16 05:19:30 CET 2009

Well, just for the fun of it...I did re-write the Ethernut 2.1b CPLD 
with verilog.  I still have not verified it yet (by burning the part on 
a board)...but here is a "pre release" version.  This is a complete copy 
of the project that was done with Webpack 9.1.

Hopefully, soon, I can give it a try.


Harald Kipp wrote:
> Jim Patchell wrote:
>> It was based on the 
>> Ethernut 2.1b dev board, with changes such as using an Actel FPGA (which 
>> will be where the hardware portion of my application will live), plus it 
>> takes the place of the Xilinx CPLD...
> Cool. Did you do the banked memory register in Verilog? If yes, would
> you be willing to contribute it under BSD license?
> You may know, that Ethernut 3 got a larger CPLD, which includes an MMC
> interface. We have all tools to compile Verilog into XSVF and upload it
> together with a small utility (called XsvfExecutor) to the target via
> Ethernet and let the CPU program the CPLD. For Ethernut 3 this works in
> one go and is quite convenient, just editing the Verilog source, typing
> 'make install' and have the new CPLD running within a few seconds.
> I'd like to have this available for Ethernut 2 as well, but currently
> the CPLD contents is defined as a schematic only, created with the ISE tool.
> Harald
> _______________________________________________
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