[En-Nut-Discussion] Clocks not working in newer releases

Ajit Narayanan ajitn at inventionlabs.in
Fri Mar 27 19:07:22 CET 2009


Hi all,

I've been trying to get some applications I'd written for older versions
of Ethernut to work on the latest stable (4.6.5) and beta (4.8.0) builds
and have been facing difficulties with some portions.

My applications are based on the TLV320AIC23B chip on a custom board which
resembles the AT91SAM7x256-EK (and uses the 7x256 microcontroller). I feed
a clock to the TLV chip from the ARM, and I use the following code to
generate the clock:

int Tlv320DacAdaptMasterClock( void )
{
    u_int pll_mul;
    u_int pll_div;
    u_int pck_pres;

    pck_pres = PMC_PRES_CLK_8; /* x256 */
    pll_mul = 538;
    pll_div = 110;

    outr(CKGR_PLLR, CKGR_USBDIV_4 | CKGR_OUT_0 | CKGR_PLLCOUNT | (pll_mul <<
CKGR_MUL_LSB) | (pll_div << CKGR_DIV_LSB));
    /* Wait until PLL is locked. */
    while ((inr(PMC_SR) & PMC_LOCK) == 0);

    /* Enable PIOB clock. */
    outr(PMC_PCER, _BV(PIOB_ID));
    /* Enable PCK2 output function at pin PB22. */
    outr(PIOB_BSR, _BV(PB22_PCK2_B));
    /* Disable PB22 PIO function. */
    outr(PIOB_PDR, _BV(PB22_PCK2_B));

    outr(PMC_PCKR2, PMC_CSS_PLL_CLK | pck_pres);
    /* Enable PCK2 output. */
    outr(PMC_SCER, PMC_PCK2);

    outr(PMC_MCKR, PMC_CSS_PLL_CLK);
    while ((inr(PMC_SR) & PMC_MCKRDY) == 0);

    return 0;
}


This function is called at the start of the program.

Works fine in version 4.4.0 but in 4.6.5 and 4.8.0, executing the above
code buggers the UARTs and dbgu.

Could anyone provide me with any insights on why this may be happening? I
suspected that the switch from supervisor to system mode which happened
sometime early this year may have caused a problem but I can't figure out
how to change the init code to test out this hypothesis.

Best,
Ajit





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