[En-Nut-Discussion] Ethernut 5 + Eclipse tutorial

[Harald Kipp]

Hi Markus,

On 21.02.2012 08:09, Markus Dost wrote:
>   and the arm-none-eabi-gdb.exe:
> 
> 	symbol-file C:\\ethernut-4.10\\nutapp\\events\\events.elf
> 	Ignoring packet error, continuing...
> 	warning: unrecognized item "timeout" in "qSupported" response
> 	Ignoring packet error, continuing...
> 	Ignoring packet error, continuing...
> 	Ignoring packet error, continuing...
> 	Ignoring packet error, continuing...
> 	Ignoring packet error, continuing...
> 	Ignoring packet error, continuing...
> 	load C:\\ethernut-4.10\\nutapp\\events\\events.elf
> 	You can't do that when your target is `None'
> 	set $pc=0x20000000
> 	No registers.
> 	tbreak main
> 	Cannot access memory at address 0x200002a4
> 	continue
> 	The program is not being run.
> 
> For me it seems that the arm-none-eabi-gdb.exe has problems to access  
> the controller.

Mh...no idea right now. I've updated the webpage

http://www.ethernut.de/en/tools/eclipse/confdebug.html

Here's my ethernut5.cfg

=======================================================================
# We add to the minimal configuration.
source [find target/at91sam9260.cfg]

# If DCC downloads are enabled, we need a work area.
# The configuration line below is intentionally commented,
# because this option may fail when code is directly loaded
# into internal SRAM. In this case you may provide another
# area, a few kB will do. The configuration below will occupy
# the complete SRAM.
#$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x8000

$_TARGETNAME configure -event reset-start {
        # At reset CPU runs at 32.768 kHz.
        # JTAG Frequency must be 6 times slower if RCLK is not supported.
        jtag_rclk 5

	# For memory access we must halt the CPU
        halt
	wait_halt

	# Optionally enable DCC downloads. If enabled,
	# a work area must be provided too (see above).
#	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads

        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
        mww phys 0xfffffd08 0xa5000501
}
	
$_TARGETNAME configure -event reset-init {
        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog

	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
        sleep 20                          ;# wait 20 ms
        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
        sleep 10                          ;# wait 10 ms
        mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
        sleep 20                          ;# wait 20 ms
        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
        sleep 10                          ;# wait 10 ms
        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
        sleep 10                          ;# wait 10 ms

	# Increase JTAG Speed to 6 MHz if RCLK is not supported
        jtag_rclk 5000

	# Fast memory access may fail, when the CPU is running
        # in slow clock mode. Intentionally disabled by default.
#	arm7_9 fast_memory_access enable

	mww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31
        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31
        
        mww 0xffffef1c 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory

	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)

	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
	mww 0x20000000 0
	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
	mww 0x20000000 0
	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
	mww 0x20000000 0
	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
	mww 0x20000000 0
	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us

#	mww 0xFFFFEF00 0x00000003         ;# MATRIX_MRCR : Remap internal SRAM to address 0
}
=======================================================================

Here is the at91sam9260.cfg

=======================================================================
######################################
# Target:    Atmel AT91SAM9260
######################################

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME at91sam9260
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
  # force an error till we get a good number
   set _CPUTAPID 0x0792603f
}

reset_config trst_and_srst separate trst_push_pull srst_open_drain

#
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

jtag_nsrst_delay 300
jtag_ntrst_delay 200

jtag_rclk 3

######################
# Target configuration
######################

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs

# Internal sram1 memory
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
=======================================================================

and finally the turtelizer2.cfg

=======================================================================
#
# egnite Turtelizer 2
#
# http://www.ethernut.de/en/hardware/turtelizer/index.html
#

interface turtle

ft2232_device_desc "Turtelizer JTAG/RS232 Adapter"
ft2232_layout turtelizer2
ft2232_vid_pid 0x0403 0xbdc8

reset_config srst_only
=======================================================================

One thing you may try is to reduce

jtag_rclk 5000

to mmmmhhhh...

jtag_rclk 1000

Just in case that there are cable problems. Btw. are you using the original red JTAG adapter board with the four header connectors?

Regards,

Harald