[En-Nut-Discussion] stm32f4_clk.c: STM32F2 and PLL configuration

[Henrik Maier]

Hello Uwe,

I am currently working on getting the STM3220G_EVAL evaluation board 
running with Nut/OS.

I stumbled across issues when sending larger Ethernet frames (> 300 
bytes) at 100Mbit/s which did not work. 10 Mbit/s was OK.

After some debugging this was solved by tweaking the PLL configuration 
to use the same values as ST's system_stm32f2xx.c for HSE 25MHz and 
SYSCLK of 120 MHz.

So once I changed the current code in stm32f4_clk.c (lines 358/359) from

    #define  PLLM (PLLCLK_IN/15000000) // PLM = 1.6666
    #define  PLLN ((144) << _BI32(RCC_PLLCFGR_PLLN_0))

to

    #define  PLLM (PLLCLK_IN/1000000) // PLLM = 25
    #define  PLLN ((240) << _BI32(RCC_PLLCFGR_PLLN_0))

the httpserv.c demo works beautifully at 100Mbit/s.

Was there a particular reason to deviate from ST's default? I am also 
wondering how you got the STEVAL_PCC010 evaluation board working at 100 
Mbit/s and why this fails for the STM3220G_EVAL as both boards seem to 
use the same clock values. Maybe because of the different phy? Could the 
DP83848 be more sensitive to clock jitter?
If your STEVAL_PCC010 evaluation board also works with above PLLM 25 
setting I wouldn't mind changing it in the trunk.
What are your thoughts?

Cheers,

Henrik