[En-Nut-Discussion] stm32f4_clk.c: STM32F2 and PLL configuration

Uwe Bonnes bon at elektron.ikp.physik.tu-darmstadt.de
Tue Feb 5 11:41:50 CET 2013

>>>>> "Henrik" == Henrik Maier <hmnews at proconx.com> writes:

    Henrik> Was there a particular reason to deviate from ST's default?

Because I worked for me? Because I didn't understand bthe documents better?
Sorry, I don't remember.

    Henrik> I am
    Henrik> also wondering how you got the STEVAL_PCC010 evaluation board
    Henrik> working at 100 Mbit/s and why this fails for the STM3220G_EVAL
    Henrik> as both boards seem to use the same clock values. Maybe because
    Henrik> of the different phy? Could the DP83848 be more sensitive to
    Henrik> clock jitter?  If your STEVAL_PCC010 evaluation board also works
    Henrik> with above PLLM 25 setting I wouldn't mind changing it in the
    Henrik> trunk.  What are your thoughts?

Did you compare the schematics? On th PCC010v2, the phy has it's own
crystal. Is the DP83848 driven by MCO out? And if yes, did you specify MCO
with as least GPIO_CFG_SPEED_FAST or probably better GPIO_CFG_SPEED_HIGH?

Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

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