[En-Nut-Discussion] Increasing the performance for Cortex-M3/M4

Michael Fischer fischermi at t-online.de
Sun Sep 8 14:04:42 CEST 2013

Hello List,

compared to the CPU init code:


the SetSysClock functionality is comment out, and an own function
in stm32f4_clk.c is used. But here the Instruction and Data
cache is not enabled.

Without the cache enabled, a network RX performance of about
32Mbit/sec could be reached on a stm3220g-eval board where the
CPU is running with 120 MHz. If both cache are enabled, a rate
of about 45MBit/sec could be reached. The new code of stm32f4_clk.c
will look like:

     rcc_reg = FLASH->ACR;
     rcc_reg &= ~FLASH_ACR_LATENCY;
     rcc_reg |= FLASH_ACR_ICEN | FLASH_ACR_DCEN; /* Enable I/D cache */
     FLASH->ACR = rcc_reg;

Best regards,

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