[En-Nut-Discussion] Increasing the performance for Cortex-M3/M4

[bon at elektron.ikp.physik.tu-darmstadt.de]

>>>>> "Michael" == Michael Fischer <fischermi at t-online.de> writes:

    Michael> Hello List, compared to the CPU init code:

    Michael> nut\arch\cm3\dev\stm\vendor\system_stm32f2xx.c
    Michael> nut\arch\cm3\dev\stm\vendor\system_stm32f4xx.c

    Michael> the SetSysClock functionality is comment out, and an own
    Michael> function in stm32f4_clk.c is used. But here the Instruction and
    Michael> Data cache is not enabled.

    Michael> Without the cache enabled, a network RX performance of about
    Michael> 32Mbit/sec could be reached on a stm3220g-eval board where the
    Michael> CPU is running with 120 MHz. If both cache are enabled, a rate
    Michael> of about 45MBit/sec could be reached. The new code of
    Michael> stm32f4_clk.c will look like:

    Michael>      rcc_reg = FLASH->ACR; rcc_reg &= ~FLASH_ACR_LATENCY;
    Michael> rcc_reg |= NUT_FLASH_LATENCY | FLASH_ACR_PRFTEN ; rcc_reg |=
    Michael> FLASH_ACR_ICEN | FLASH_ACR_DCEN; /* Enable I/D cache */
    FLASH-> ACR = rcc_reg;

Looks good!

PS.: Think about us unixoids. Use '/' and not '\' as path delimiter!
-- 
Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

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