[En-Nut-Discussion] Ethernut 2.0 Alpha Schematic

[Alastair Jeremy]

Oh yeah, and before your wife shells out too much for a CPLD programmer - I
had a laugh a while back when the Altera representative told me that the
download cable for their chips would cost about US$150. It's a 25 pin plug,
a 74LS244, about 7 resistors, and a bit of ribbon cable. At least my Altera
rep also was also sensible enough to actually tell me it wasn't worth it,
without being prompted...

Alastair


-----Original Message-----
From: en-nut-discussion-admin at egnite.de
[mailto:en-nut-discussion-admin at egnite.de]On Behalf Of Austin Schutz
Sent: Thursday, 24 October 2002 10:54 AM
To: en-nut-discussion at egnite.de
Subject: Re: [En-Nut-Discussion] Ethernut 2.0 Alpha Schematic


On Wed, Oct 23, 2002 at 05:03:43PM +0200, Harald Kipp wrote:
> Here's my version of address decoding:
>
> CS = SRAM chip select
> BSx = Bank select register outputs
> SAx = SRAM address lines
> Ax = CPU address lines
>
> CS = !(A14 & A15);
> SA18 = BS4 & A15;
> SA17 = BS3 & A15;
> SA16 = BS2 & A15;
> SA15 = BS1 & A15;
> SA14 = (BS0 & A15) # (!A15 & A14);
>
> & means logical and
> # means logical or
> ! means logical negation
>
> Looks correct to me. Would you agree?
>

	Yeah, makes sense. I missed the 0x4000-0x7fff case. Ok, one more
try at the schematic (attached).
	I removed the NANDs attached to a14 and a15. Kept confusing myself.
Instead, I added a 2to4 decoder. If 14 and 15 are high, the 4to16 decoder
is enabled, otherwise the sram is enabled.
	The Y1 pin on the 2to4 decoder represents !(!A15 & A14), which
gets inverted by IC1C. The output of IC3A is (BS0 & A15), so the output of
IC9A
is (BS0 & A15) # (!A15 & A14).

	It would be nice to be able to remove one of the chips, if there's
a more clever design. 6 new chips is going to take up a lot of space.
Of course the ability to easily add several new memory mapped devices and
use bank switching should be pretty handy.


> Note, that this doesn't include bank
> select register addressing, just SRAM.
>
> The low 32k SRAM is always visible at 0x1100 to
> 0x7FFF.

	Where does 0x0000 to 0x10ff go? I've actually disabled the atmega
(and latch) on my ethernut in order to use an external 8051 ICE I have.

> The remaining 30 pages of 16k each are
> mapped at 0x8000 to 0xBFFF. From 0xC000 to 0xFFFF
> the SRAM is deselected (z-state). Of course, real
> chips use !CS.

	Right.
>
> All remaining addresses A0 to A13 are directly
> connected to SA0 to SA13.
>
	Yeah.

> I think using gates instead of z-state register
> outputs with pull downs could be better transformed
> to a CPLD. But I don't know much about CPLD
> capabilities.
>

	Not a bad idea. It looks like low end CPLDs cost about $2 US or so.
It wouldn't surprise me if you could replace most (or all) of the other
chips this way. I also don't have any experience with them, though.
	Hmm, maybe I'll ask my wife for a CPLD programmer for my birthday :-)

	Austin

_______________________________________________
En-Nut-Discussion mailing list
En-Nut-Discussion at egnite.de
http://www.egnite.de/mailman/listinfo/en-nut-discussion