[En-Nut-Discussion] CPLD Power-Up Problem

Uwe Bonnes bon at elektron.ikp.physik.tu-darmstadt.de
Wed Oct 31 12:54:22 CET 2007

>>>>> "Harald" == Harald Kipp <harald.kipp at egnite.de> writes:

    Harald> One of our customers is using a custom board based on the
    Harald> Ethernut 2.1 design. By using a specific power supply with a
    Harald> very specific voltage raise, the boards fails during
    Harald> initialization. Pulling the hardware reset doesn't help. Cycling
    Harald> just the CPLD power supply before toggling the hardware reset
    Harald> line re-awakes the board. Obviously the initial CPLD power-up
    Harald> sequence fails. On the XC9500XL series the CPLD configuration is
    Harald> loaded from EEPROM to RAM during power-up.

    Harald> As the CPU is running fine, but simply fails to access external
    Harald> memory addresses, I tried to fix this problem by letting the CPU
    Harald> re-initializing the CPLD via JTAG commands. So far this never
    Harald> worked.  But my JTAG code may still contain bugs.

    Harald> Anyone of you experienced similar CPLD problems? Any idea, how
    Harald> else to solve this?

    Harald> Btw. AFAIK the original Ethernut board does not seem to have
    Harald> this problem. At least not when using the same power supply.

Do the CPLDs still work? Do they run very hot? I had a design with XC95144XL
with pins connected to VCC. VCC had overshoots to 5.4 Volt, and that kill
the CPLDs.

Otherwise Xilinx has nearly no restrictions on power-up, so perhaps recheck
the logic to see if the CPLD doesn't "hang" on some unexpected event during
power up.

Perhaps try to look at the Pin states with some JTASG boundary scan,
e.g. mitoujtag.

Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

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