[En-Nut-Discussion] Address space of EIR

[tgrauss at free.fr]

Selon Bernd Walter <enut at cicely.de>:

> > On Sun, Oct 12, 2008 at 08:20:19PM +0200, Ole Reinhardt wrote:
> > Hello,
> >
> > > I am looking at the schematic of the EIR board and there is something I
> find
> > > strange ...
> >
> > I'll try to answer at least the first question even if I don't have the
> > EIR schematic.
> >
> > > How can I use the address bus on this board? The A0 bit is used for DQML
> and not
> > > as an address line. So the address is from A1 to A15 instead of A0 to
> A15. I can
> > > understand from A0 to A14 (15 bits instead of 16 bits addressing).
> >
> > I think the data bus is not 8 but 16 bit or even 32 bit wide. In this
> > case you can only address every 2nd or 4th address over the address bus
> > and every memory access is 2 or 4 byte aligned. In this case the first
> > or first two address lines are not needed.
>
> There is nothing strange in it once you know how SDRAM works.
> Addressline usage with the SDRAM controller is different than with the
> static memory controller - it uses a different bit layout and it uses
> multiplex addressing.
> See the Atmel datasheet, which contains some SDRAM wiring samples.
> Once a board designer has selected a memory chip there is just a single
> fixed wiring to the AT91, so everything is in the datasheet.
>
> --
> B.Walter <bernd at bwct.de> http://www.bwct.de
> Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.
> _______________________________________________
> http://lists.egnite.de/mailman/listinfo/en-nut-discussion
>

Thank you to both of you for your first hints. I will have a look in this
direction.