[En-Nut-Discussion] SVN Trunk Rev. 5422 breaks GPIO for LPC

bon at elektron.ikp.physik.tu-darmstadt.de bon at elektron.ikp.physik.tu-darmstadt.de
Sun Oct 20 19:51:53 CEST 2013

>>>>> "Ole" == Ole Reinhardt <ole.reinhardt at embedded-it.de> writes:

    Ole> Hi Uwe, unfortunately you latest commit (r5422) breaks GPIO on the
    Ole> LPC.

    Ole> My initial version implemented GpioPinSet by writing to the FIOSET
    Ole> register for high values and FIOCLR for low values. You replaced it
    Ole> by writing either 1 or 0 to the FIOSET register, which will not
    Ole> work as you can only write ones to these registers, writing 0 won't
    Ole> modify the register.

    Ole> According to the documentation it would be possible to directly
    Ole> write the final value to the FIOPIN register. Due to a silicon bug
    Ole> this is highly discouraged to do so, using the bit banding register
    Ole> access.

    Ole> If you would write two values using bit band access to the FIOPIN
    Ole> register directly one after the other, then the first access might
    Ole> get missed.

    Ole> Conclusion:

    Ole> We have to stay with the access to FIOSET and FIOCLR register.

    Ole> For now I reverted your last checkin in rev. 5423. Could you please
    Ole> point out your initial intention?

My intention was to add "do{xxx; } while 0" as otherwise things get

Sorry for not reading the initial code intense enough. Will you add or
should I or do you need more explanations for the need of the "do{xxx; }
while 0" expression?

Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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